TDA1541 PDF

It is funny for a mere electronic component to be worshiped like an object of religion, but this chip is such rare case. Augmented by the fact, that they are no more in production. These wonderful people spent considerable time researching good CD sound and they all like me reached the conclusion that the good old TDAA DAC is still the one to beat. They all use it with non-oversampling mode at 44,1 kHz sampling rate and some of them use tube output too.

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It was produced in the year , week What is DEM? To put it simply, DEM patented by R. When and where was the TDA produced? The TDA non -A was launched from to , and it had no grades. The TDAA was produced from to Final assembly was at plants in Holland, Taiwan, China or India.

What grades does the TDAA have? What does the grades mean? The S versions are guaranteed by Philips for this performance, but that does not mean that non S grades can not match the same performance level. Apart from S grades there is also R1 grade. There will still be intrinsic errors in DAC linearity due to the tolerance in the alignments of the various masks during the IC production process. As further fine-tuning of the DACs is not possible, Philips has adopted a grading process to pick out those which offer the best performance.

When the finished doped and etched silicon wafer emerges from the semi-conductor plant, it carries many dozens of individual DACs.

A computer-controlled tester, consisting of 28 needle probes, then connects to the appropiate pads on each raw DAC die, providing power and supplying serial data from a CD player. Automatic machinery then slices the wafer into the individual dies and mounts those that passed the initial test in the familiar pin DIL plastic package.

At this stage, the finished TDA ICs are graded by a computer-controlled test station into three classes. SC, NO. In the binary weighted current network a dynamic current divider is used to obtain the required high accuracy of the six most significant bits without any adjustment proeedure or trimming techniqne.

To construct the ten least significant bits a new approach is used to construct the passive divider stage based on emitter sealing of transistors.

As the bk switches are optimized for fast-settling and low-glitch current, both converters can be used without extra sample-and-hold or degtitcher circuitry at sampling frequencies up to kHz. The converter has a differential linearity of 0. The high linearity of the converter results in a distortion of 0.

The chip is processed in a standard bipolar process and the die size is 3. Oversampling techniques allow digital filtering, which eliminates the need for high-order analog low-pass post-filtering. Phase distortion can affect the stereo information at the high-end of the audio band. Furthermore, oversampling increases the dynamic range of the converter which allows for a digital implementation of tone-control systems.

The extra sample and hold must be applied to avoid phase differences between the two channels at high frequencies. Another technique uses laser trimming [2], sometimes combined with an increase in process complexity to obtain the required accuracy [3]. This principle combines passive division with a dynamic system to improve accuracy in a standard process. Moreover, the bit current switches can easily be optimized for fast settling with a low-glitch energy in such a way that both converters can be used without external sample-and-hold or deglitcher circuitry.

In order to minimize the number of pins needed for the external capacitors, a rather unusual approach is used to construct the remaining ten binary weighted bit currents. The principle uses emitter scaling of transistors and is based on the basic statistical rule that the relative accuracy improves with the square root of the numbers involved, assuming an uncorrelated distribution between the transistor matching.

Figure 1 II. The reference current source that is common for the two identical converters is fed to three 2-bit dynamic divider stages which perform the required accuracy for the six most significant bits. One output current of the last dynamic divider is fed to the bit passive divider.

To minimize timing errors the converter contains on-chip data latches. In order to obtain a low capacitive feedthrough the data input is in a serial mode which requires only four input pins. The digital inputs are TTL compatible and the circuit accepts two different data input formats. An internal emitter-coupled oscillator supplies the dynamic divider stages with the necessary control signals. In the internal digital part a low-voltage swing unsaturated current-mode logic CML is used for speed and low-interference noise.

However, in digital audio applications the dc stability of the reference source is not that important since this temperature depefidence only leads to 0. Figure 2 Figure 3 IV. However, in high-resolution converters this principle sets a high demand on the relative accuracy of the bit currents. To obtain the required accuracy of the six most significant binary weighted bit currents, dynamic element matching is used. The reference current is divided into four nearly equal parts by means of a passive current divider using resistor matching.

The four currents are interchanged during equal time intervals controlled by an internal shift register. The output currents of this dynamic divider stage alll have the same average value with a relative error which ecluals the resistor matching accuracy times the timing accuracy of the interchanging network. A more complete description of dynamic current division is provided in [4].

Two of these interchanged currents are added to construct the most significant bit current. The third one is fed directly to the bit switches, while the fourth current flows through a second identical dynamic stage. Three of these dynamic divider stages are needed to construct the six MSB currents. The interchanging network consists of Darlington differential pairs which are optimized for base current losses and interchanging frequency.

The clock frequency of the interchanging shift register is not related to the sample frequency and is generated by a free-running emitter-ccnpled oscillator which operates at about kHz without affecting the accuracy. A simple low-pass filter is used to remove the ripple of the bit currents due to the interchanging operation to obtain the accuracy and is only drawn here for the MSB.

This approach requires seven noncritical external ceramic cttpacitors for each channel. Furthermore, the thermal noise on the bit currents is reduced by the filtering operation down to dB below the maximum output level of the converter. The Darlington stages isolate the filter operation from switching transients of the bit switches.

One output current of the last dynaniic divider is fed to the new bit passive divider. This concept is used for the remaining ten least significant bits. It only consists of Darlington transistors and does not require any trimming or adjustment procedure and operates over a large temperature range. In this way the input current Iin is divided into equal currents with a value of one LSB.

The output current of the MSB bit of this passive divider is constructed by a combination of collector currents. The required accuracy can only be obtained by carefully randomizing the transistors over the passive current divider surface to eliminate temperature gradients and to minimize mask errors.

Assuming a Gaussian distribution between the offset voltages of the transistors, the relative accuracy of the coflector current improves, according to statistics, with the square root of the number of transistor pairs involved.

Due to offset-binary coding, the largest glitch occurs at the zero crossing of the analog output signal. To avoid differences in base current losses owing to the different bit currents, the six most significant bits are switched with a fast diode-transistor switch, as is shown in Fig. The diode-transistor switch is controlled by data latches and driven by a differential amplifier.

At the emitter node of the switch a voltage swing of half the collector swing is present. To avoid long settling times due to the parasitic load Zout, a cascode stage is added. To further minimize this parasitic load and to preserve the current generation network from switching transients, an extra cascode stage is added.

The next four bit currents are switched with compensated diode-transistor switches, as shown in Fig. This compensation is added to cancel the voltage swing at the current source connection which causes long settling times as these bit currents are small to discharge the parasitic capacitors. When the bit current is drained to Vref, an extra current Icomp is added to the current source connection and this causes an extra voltage drop over the resistor R, which cancels the voltage swing at the emitter node.

During switching transients a small amount of compensation current flows into the output line of the converter. An error in the bit current could be introduced depending on the magnitude of the compensation current and the time duration of the current transient. The charge contribution of this current transient can be compared with the charge contribution of one LSB current during one sample period 4 The compensation current in the bit switch has about the same magnitude as the bit current itself.

To avoid large glitches in the output current this switching method is not used for the six most significant bits. The six least significant bits are switched to the output line with differential pairs, which are compensated for base current losses.

Normally an operational amplifier will be applied for this purpose. This standard provides an easy interfacing between digital signal processing devices, operating at various word lengths. In this standard three signals are used. The first one is the DATA signal. It consists of a sample of the right channell followed by a sample of the left channel. Any bit length is allowed although the MSB must be the first one. It is not only used to clock the DATA bits into the input latches, but also to determine exactly the moment at which the sample value appears at the output.

In this mode the DATA signals of the left and right channel are applied simultaneously to two different input pins. Only one bit clock signal is used to clock both data signals into the converter. The positive slope of the latch enable signal is used to indicate the end of the data input action and to determine the moment at which the outputs change their sample values.

This input format is especially suited for those cases in whi;h the circuits in front of the DAC use a nonstandard serial format. Total glitch charge is within 0. The feedback resistor of the operational amplifier converts the output current of the converter into a voltage and a low-pass output levels. A HP A measurement set is used for the measurement of signal-to-noise and total harmonic distortion. An address generator selects the succeeding samples, depending on the desired frequency, in such a way that the quantizing error has no correlation with the sine wave.

A 13th-order symmetrical filter with O. Furthermore, the filter must have a sufficiently low distortion to avoid that measurement results are being affected. The sample frequency is At full scale hardly any decrease in signal-to-noise ratio with respect to the bit theoretical curve is found. The converter is used four times oversampled with a sample frequency of

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