Typical applications cover off line power supplies with a secondary power capability 25W in wide range condition and 50W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the possibility to operate in stand-by mode without extra components. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. Primary side circuit common ground connection.
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Typical applications cover offline power supplies with a secondary power capability of 25W in wide range condition and 50W in single range or with doubler configuration. Burst mode operation is an additional feature of this device, offering the ability to operate in stand-by mode without extra components.
Table 3. It provides internal bias current during start-up via an integrated high voltage current source which is switched off during normal operation. The device is able to handle an unclamped current during its normal operation, assuring self protection against voltage surges, PCB stray inductance, and allowing a snubberless operation for low output power. Primary side circuit common ground connection.
After that, the current source is shut down, and the device tries to start up by switching again. This pin is also connected to the error amplifier, in order to allow primary as well as secondary regulation configurations. In case of primary regulation, an internal 13V trimmed reference voltage is used to maintain VDD at 13V.
For secondary regulation, a voltage between 8. The COMP pin behaves as a constant current source, and can easily be connected to the output of an optocoupler. Note that any overvoltage due to regulation loop failure is still detected by the error amplifier through the VDD voltage, which cannot overpass 13V.
The output voltage will be somewhat higher than the nominal one, but still under control. Its bandwidth can be easily adjusted to the needed value with usual components value. As stated above, secondary regulation configurations are also implemented through the COMP pin. When the COMP voltage is going below 0. This feature can be used to switch off the converter, and is automatically activated by the regulation loop no matter what the configuration is to provide a burst mode operation in case of negligible output power or open load condition.
It provides also a synchronisation capability, when connected to an external frequency source. Figure 1. Thus, the outer voltage control loop defines the level at which the inner loop regulates peak current through the power switch and the primary winding of the transformer.
Excellent open loop D. This results in improved line regulation, instantaneous correction to line changes, and better stability for the voltage regulation loop. Current mode topology also ensures good limitation in case there is a short circuit. During the first phase the output current increases slowly following the dynamic of the regulation loop. Then it reaches the maximum limitation current internally set and finally stops because the power supply on VDD is no longer correct. For specific applications the maximum peak current internally set can be overridden by externally limiting the voltage excursion on the COMP pin.
This function prevents anomalous or premature termination of the switching pulse in case there are current spikes caused by primary side capacitance or secondary side rectifier reverse recovery time.
FSW is the normal switching frequency. ISTBY is the minimum controllable current, corresponding to the minimum on time that the device is able to provide in normal operation. Note: that PSTBY may be affected by the efficiency of the converter at low load, and must include the power drawn on the primary auxiliary voltage. This situation leads to the shutdown mode where the power switch is maintained in the Off state, resulting in missing cycles and zero duty cycle.
The above cycle repeats indefinitely, providing a burst mode of which the effective duty cycle is much lower than the minimum one when in normal operation. The equivalent switching frequency is also lower than the normal one, leading to a reduced consumption on the input main supply lines.
The output voltage remains regulated around the normal level, with a low frequency ripple corresponding to the burst mode. The amplitude of this ripple is low, because of the output capacitors and low output current drawn in such conditions.
This current is partially absorbed by internal control circuits which are placed into a standby mode with reduced consumption and also provided to the external capacitor connected to the VDD pin.
As soon as the voltage on this pin reaches the high voltage threshold VDDon of the UVLO logic, the device becomes active mode and starts switching. The start-up current generator is switched off, and the converter should normally provide the needed current on the VDD pin through the auxiliary winding of the transformer, as shown on see Figure In case there are abnormal conditions where the auxiliary winding is unable to provide the low voltage supply current to the VDD pin i.
The converter enters a endless start-up cycle, with a startup duty cycle defined by the ratio of charging current towards discharging when the device tries to start. This low value start-up duty cycle prevents the application of stress to the output rectifiers as well as the transformer when a short circuit occurs. The external capacitor CVDD on the VDD pin must be sized according to the time needed by the converter to start up, when the device starts switching.
This time tSS depends on many parameters, among which transformer design, output capacitors, soft start feature, and compensation network implemented on the COMP pin.
Worst case is generally at full load. The soft start feature can be implemented on the COMP pin through a simple capacitor which will be also used as the compensation network.
In this case, the regulation loop bandwidth is rather low, because of the large value of this capacitor. In case a large regulation loop bandwidth is mandatory, the schematics of see Figure 17 can be used. It mixes a high performance compensation network together with a separate high value soft start capacitor. Both soft start time and regulation loop bandwidth can be adjusted separately. This voltage can be used for supplying external functions, provided that their consumption does not exceed 0.
Once the "Shutdown" signal has been activated, the device remains in the Off state until the input voltage is removed. CO MP 1? More complex impedance can be connected on the COMP pin to achieve different compensation level.
A capacitor will provide an integrator function, thus eliminating the DC static error, and a resistance in series leads to a flat gain at higher frequency, insuring a correct phase margin.
This configuration is illustrated in Figure 20 As shown in Figure 19 an additional noise filtering capacitor of 2. Figure 21 shows such a configuration. Note: R1 and C2 build the classical compensation network, and Q1 is injecting the slope compensation with the correct polarity from the oscillator sawtooth. Figure 21 shows one possible schematic to be adapted, depending the specific needs. If the proposed schematic is used, the pulse duration must be kept at a low value ns is sufficient for minimizing consumption.
The optocoupler must be able to provide 20mA through the optotransistor. The minimum junction temperature at which over-temperature cut-out occurs is ? C, while the typical value is ? The device is automatically restarted when the junction temperature decreases to the restart temperature threshold that is typically 40?
Undervoltage Lockout Figure 5. Transition Time Figure 8. Breakdown Voltage vs. Temperature Figure Typical Frequency Variation 1. Mixed Soft Start and Compensation Figure Following the Layout Considerations is sufficient to prevent catastrophic damages most of the time. However in some cases, the voltage surges coupled through the transformer auxiliary winding can exceed the VDD pin absolute maximum rating voltage value.
Such events may trigger the VDD internal protection circuitry which could be damaged by the strong discharge current of the VDD bulk capacitor. The simple RC filter shown in Figure 23 can be implemented to improve the application immunity to such surges. Figure They may be classified into two categories: — Minimizing power loops: The switched power current must be carefully analysed and the corresponding paths must be as small an inner loop area as possible. This avoids radiated EMC noises, conducted EMC noises by magnetic coupling, and provides a better efficiency by eliminating parasitic inductances, especially on secondary side.
C6 must be as close as possible to T1. Signal components C2, ISO1, C3, and C4 are using a dedicated track connected directly to the power source of the device. These packages have a Lead-free second level interconnect. The maximum ratings related to soldering conditions are also marked on the inner box label. Dim Min. A, Feb. End Start Top cover tape mm min Empty components pockets saled with cover tape.
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Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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