DM74LS161AN DATASHEET PDF

Features, Applications These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform.

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These synchronous, presettable counters feature an inter- nal carry look-ahead for application in high-speed counting designs. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is pro- vided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating.

This mode of operation eliminates the output counting spikes which are normally associated with asynchronous ripple clock counters. A buffered clock input triggers the four flip-flops on the rising positive-going edge of the clock input waveform.

These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable input.

The clear function for the DM74LSA is asynchro- nous; and a low level at the clear input sets all four of the flip-flop outputs LOW, regardless of the levels of clock, load, or enable inputs. The clear function for the DM74LSA is synchronous; and a low level at the clear inputs sets all four of the flip-flop outputs LOW after the next clock pulse, regardless of the levels of the enable inputs.

This synchronous clear allows the count length to be modified easily, as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to all low outputs. Ordering Code: Devices also available in Tape and Reel. Order Number.

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